1. Field of the Invention
This invention relates to semiconductor memory devices, and more particularly to a semiconductor memory device such as a DRAM (dynamic random access memory) device which uses memory cells each composed of a transfer transistor and a tree-type capacitor for data storage.
2. Description of the Related Art
FIG. 1 shows a schematic circuit diagram of a single memory cell of a DRAM device, which includes a transfer transistor T and a data storage capacitor C that can retain thereon electric charge representative of data. The transfer transistor T includes a source connected to a corresponding bit line BL, a drain connected to a storage electrode 6 of the data storage capacitor C, and a gate connected to a corresponding word line WL. Further, the data storage capacitor C has an opposed electrode 8 connected to a constant power source and a dielectric film 7 formed between the storage electrode 6 and the opposed electrode 8.
In conventional DRAMs having a storage, capacity less than 1 Mbit (megabit), it is a customary practice to use a two-dimensional capacitor called a planar-type capacitor as the data storage capacitor. However, a drawback of the planar-type capacitor is that its structure takes up quite a large surface area in order to store an adequate amount of charge to reliably represent data. The planar-type capacitor is therefore not suitable for DRAM devices having a high degree of integration. In large scale integration DRAMs, such as DRAMs with 4M or higher, a three-dimensional capacitor, e.g., a stacked-type or a trench-type capacitor, is used as the data storage capacitor.
The stacked-type or the trench-type capacitor allows a large amount of electric charge representative of data to be stored thereon, even if the feature size of the DRAM device is downsized for large scale integration. However, for VLSI (very-large-scale integration) DRAMs such as 64M DRAMs, the stacked-type and trench-type capacitors can no longer provide adequate charge storage areas for the data storage capacitors for reliable data retaining capability.
One solution to the foregoing problem is to utilize the so-called fin-type stacked capacitor. Such capacitors, are described, for example, in a paper entitled "3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMs" by Ema et al. in International Electron Devices Meeting, pp. 592-595, December 1988. The fin-type stacked capacitor is composed of electrodes and dielectric films that are formed into a fin-like structure having a plurality of stacked layers that allow an increased surface area for the storage electrodes. Various patents have issued which relate to the fin-type stacked capacitor, including U.S. Pat. Nos. 5,071,783; 5,126,810; 5,196,365; and 5,206,787.
Another solution is to utilize the so-called cylindrical-type stacked capacitor. This type of capacitor is described, for example, in a paper entitled "Novel Stacked Capacitor Cell for 64-Mb DRAM", by Wakamiya et al. on 1989 Symposium on VLSI Technology Digest of Technical Papers, pp. 69-70. The cylindrical-type stacked capacitor is composed of electrodes and dielectric films that are formed into an upright extended cylindrical shape which can increase the surface area of the storage electrodes. Various patents have been issued which relate to the cylindrical-type stacked capacitor, including U.S. Pat. No. 5,077,688.
With the trend toward larger and larger scale integration, the feature size of a single DRAM cell is correspondingly reduced. However, this also causes a reduction in the surface area, and thus the capacitance, of the data storage capacitor. A small capacitance for the data storage capacitor would make the DRAM device more likely to incur soft errors, for example, due to the incidence of .alpha.-rays. Therefore, there still exists a need in the semiconductor industry for a new and improved stricture for the data storage capacitors of DRAM devices, that can nonetheless allow the data storage capacitors to have an adequate capacitance for reliable data storage when the DRAM cells are downsized for higher integration.